Error propagation and recovery in decision-feedback equalizers for nonlinear channels

©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Nonlinear intersymbol interference is often present in communication and digital storage channels. Decision-feedback equalizers (DFEs) can decrease this nonlinear effect by including appropriate nonlinear feedback filters. Although various applications of these types of equalizers have been published in the literature, the analysis of their stability and error recovery has not appeared. We consider a DFE with a nonlinear feedback filter based on a discrete Volterra series. We extend error propagation, error probability, stability, and error recovery time results for Nth order nonlinear channelsTsimbinos, J. White, L.B

Improved error table compensation of A/D convertors using pseudorandom calibration signals

A previously published technique using sinusoidal calibration signals to generate error tables for linearizing A/D convertors suffers from limited compensation performance due to incomplete error table coverage. The authors show that better coverage and improved compensation may be achieved by using pseudorandom calibration signals. The techniques is illustrated by using state-space error tables to reduce the nonlinear distortion of an A/ D convertor sampler model representing input dependent timing jitter

Results of A/D converter compensation with a VLSI chip

© Copyright 2002 IEEEError table compensation is one technique that can be used to improve the spurious free dynamic range of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, some additional on chip circuits, and a lookup table that is stored in external memory. The 10 GOPS transversal filter differentiator chip was designed and fabricated in a 0.35 /spl mu/m CMOS process, has programmable tap weights, and can operate at a maximum clock rate of 200 MHz. The results of this paper show that this error table compensation system is capable of providing up to 13 dB improvement in the dynamic range of typical high speed A/D converters. This may result in more reliable detection of weak signals of interest

A VSLI chip implementation of an A/D converter error table compensator

Copyright © 2001 Elsevier ScienceError table compensation can be used to improve the spurious free dynamic range performance of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, additional on-chip circuits including delays and an adder, and a lookup table that is stored in external memory. The cascadable 10GOPS transversal filter differentiator chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti-symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4-2 compressors to reduce the transistor count. The chip was fabricated in a 0.35-μm CMOS process, measures 3.1 × 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz. It is shown that the error table compensation system is capable of providing between 7 and 13 dB improvement in the dynamic range of typical high-speed A/D converters. © 2001 Elsevier Science B.V. All rights reserved.A. Beaumont-Smith, J. Tsimbinos, C. C. Lim and W. Marwoodhttp://www.elsevier.com/wps/find/journaldescription.cws_home/505607/description#descriptio